- Pay$160,000–290,000 per year
- HoursFull-time
- WhereHawthorne, California
- WorkOn-site
- TermsFull-time
- ExperienceExperienced · 5+ years
- ReferenceRef. 8306
- In the paper untilThu 19 Nov
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About the job
Full-time, onsite. 5+ years of FPGA RTL design, including Verilog, SystemVerilog, and AMD Vivado. Bachelor's degree and U.S. Person status required. Medical, dental, and vision benefits fully paid. 401(k) match, free daily lunch, equity, and unlimited PTO.
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