- Pay$160,000–290,000 per year
- WhereHawthorne, California, United States
- WorkOn-site
- TermsFull-time
- Experience5+ years
- ReferenceRef. 8165
- In the paper untilThu 19 Nov
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About the job
Full-time, on-site. 5+ years of FPGA RTL design experience. Bachelor's degree and U.S. person status required. Verilog, SystemVerilog, AXI, and Vivado experience. Health, dental, and vision benefits. 401(k) match. Stock options. Unlimited PTO.
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Found on boards.greenhouse.io. Not placed by the employer; applications go to the original posting.